1. Technical Field of the Invention
This invention relates generally to data communications and more particularly to limiting circuits within receivers of such data communications.
2. Description of Related Art
Communication systems are known to transport large amounts of data between a plurality of end user devices, which, for example, include telephones, facsimile machines, computers, television sets, cellular telephones, personal digital assistants, etc. As is also known, such communication systems may be local area networks (LANs) and/or wide area networks (WANs) that are stand-alone communication systems or interconnected to other LANs and/or WANs as part of a public switched telephone network (PSTN), packet switched data network (PSDN), integrated service digital network (ISDN), the Internet, etc. As is further known, communication systems include a plurality of system equipment to facilitate the transporting of data. Such system equipment includes, but is not limited to, routers, switches, bridges, gateways, protocol converters, frame relays, private branch exchanges, etc.
The transportation of data within communication systems is typically governed by one or more standards that ensure the integrity of data conveyances and fairness of access for data conveyances. For example, there are a variety of Ethernet standards that govern serial transmissions within a communication system at data rates of 10 megabits per second, 100 megabits per second, 1 gigabit per second and beyond. Another standard, which is for fiber optic data conveyances, is Synchronous Optical NETwork (SONET) that includes a hierarchy of data rates such as OC-3=155 Mbps, OC-12=644 Mbps, OC-48=2.488 Gbps, OC-192=9.952 Gbps, and OC-768=39.808 Gbps. In accordance with such standards, many system components and end user devices of a communication system transport data via serial transmission paths. Internally, however, the system components and end user devices process data in a parallel manner. As such, each system component and end user device must receive the serial data and convert the serial data into parallel data without loss of information.
To receive data, the system component includes a receiver section that may include an equalization module, a limiter, and a clock and data recovery module. As is known, the equalization module filters incoming serial data based on an equalization response, which typically corresponds to an inverse of the channel response of the channel on which the data was received. The limiter limits, on a bit-by-bit basis, the incoming data to one of the known states of the data symbol (e.g., a 1 or a 0 for a binary data symbol). The clock and data recovery module recovers a clock signal and data from the limited symbols produced by the limiter. The recovered data is then converted into a parallel data stream for subsequent processing.
One known implementation of a limiter is disclosed in a paper by Galal and Razavi, entitled, “10 Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18 μm CMOS Technology”. Such a limiter works well in small signal applications. However, as signal magnitude increases, the feedback stage introduces distortion, in the form of jitter, due to severe reverse biasing of the gate-source voltages of its transistors. The introduced jitter reduces the receiver sensitivity, which limits the amount of data and/or the distance over which data can be transmitted.
Therefore, a need exists for a limiting circuit that includes a feedback stage with negligible introduction of jitter.